Microchip Technology Inc. ATSAMD21E15CU 2024.11.10 Microchip ATSAMD21E15CU device: Cortex-M0+ Microcontroller with 32KB Flash, 4KB SRAM, 35-pin package CM0+ r0p1 little 2 false 8 32 AC Analog Comparators AC 0x42004400 0x0 0x40 registers n AC 24 COMPCTRL0 Comparator Control n 0x20 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Enable 19 1 INTSEL Interrupt Selection 5 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 2 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 OUT Output 16 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 SINGLE Single-Shot Mode 1 1 SPEED Speed Selection 2 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x1 SWAP Swap Inputs and Invert 15 1 COMPCTRL1 Comparator Control n 0x34 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYST Hysteresis Enable 19 1 INTSEL Interrupt Selection 5 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 2 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 OUT Output 16 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 SINGLE Single-Shot Mode 1 1 SPEED Speed Selection 2 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x1 SWAP Swap Inputs and Invert 15 1 CTRLA Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 LPMUX Low-Power Mux 7 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 write-only CTRLB Control B 0x1 8 write-only n 0x0 0xFFFFFFFF START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x2 16 read-write n 0x0 0xFFFFFFFF COMPEI0 Comparator 0 Event Input 8 1 COMPEI1 Comparator 1 Event Input 9 1 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0xFFFFFFFF COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0xFFFFFFFF COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0xFFFFFFFF COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 SCALER0 Scaler n 0x40 8 read-write n 0x0 0xFFFFFFFF VALUE Scaler Value 0 6 SCALER1 Scaler n 0x61 8 read-write n 0x0 0xFFFFFFFF VALUE Scaler Value 0 6 STATUSA Status A 0x8 8 read-only n 0x0 0xFFFFFFFF STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x9 8 read-only n 0x0 0xFFFFFFFF READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only SYNCBUSY Synchronization Busy 7 1 STATUSC Status C 0xA 8 read-only n 0x0 0xFFFFFFFF STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 WINCTRL Window Control 0xC 8 read-write n 0x0 0xFFFFFFFF WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 ADC Analog Digital Converter ADC 0x42004000 0x0 0x2C registers n ADC 23 AVGCTRL Average Control 0x2 8 read-write n 0x0 0xFFFFFFFF ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa CALIB Calibration 0x28 16 read-write n 0x0 0xFFFFFFFF BIAS_CAL Bias Calibration Value 8 3 LINEARITY_CAL Linearity Calibration Value 0 8 CTRLA Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 CTRLB Control B 0x4 16 read-write n 0x0 0xFFFFFFFF CORREN Digital Correction Logic Enabled 3 1 DIFFMODE Differential Mode 0 1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV4 Peripheral clock divided by 4 0x0 DIV8 Peripheral clock divided by 8 0x1 DIV16 Peripheral clock divided by 16 0x2 DIV32 Peripheral clock divided by 32 0x3 DIV64 Peripheral clock divided by 64 0x4 DIV128 Peripheral clock divided by 128 0x5 DIV256 Peripheral clock divided by 256 0x6 DIV512 Peripheral clock divided by 512 0x7 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 DBGCTRL Debug Control 0x2A 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run 0 1 EVCTRL Event Control 0x14 8 read-write n 0x0 0xFFFFFFFF RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event In 0 1 SYNCEI Synchronization Event In 1 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x24 16 read-write n 0x0 0xFFFFFFFF GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x10 32 read-write n 0x0 0xFFFFFFFF GAIN Gain Factor Selection 24 4 GAINSelect 1X 1x 0x0 2X 2x 0x1 4X 4x 0x2 8X 8x 0x3 16X 16x 0x4 DIV2 1/2x 0xf INPUTOFFSET Positive Mux Setting Offset 20 4 INPUTSCAN Number of Input Channels Included in Scan 16 4 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 GND Internal Ground 0x18 IOGND I/O Ground 0x19 PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 PIN16 ADC AIN16 Pin 0x10 PIN17 ADC AIN17 Pin 0x11 PIN18 ADC AIN18 Pin 0x12 PIN19 ADC AIN19 Pin 0x13 TEMP Temperature Reference 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 PIN8 ADC AIN8 Pin 0x8 PIN9 ADC AIN9 Pin 0x9 PIN10 ADC AIN10 Pin 0xa PIN11 ADC AIN11 Pin 0xb PIN12 ADC AIN12 Pin 0xc PIN13 ADC AIN13 Pin 0xd PIN14 ADC AIN14 Pin 0xe PIN15 ADC AIN15 Pin 0xf INTENCLR Interrupt Enable Clear 0x16 8 read-write n 0x0 0xFFFFFFFF OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 WINMON Window Monitor Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x17 8 read-write n 0x0 0xFFFFFFFF OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF OVERRUN Overrun 1 1 RESRDY Result Ready 0 1 SYNCRDY Synchronization Ready 3 1 WINMON Window Monitor 2 1 OFFSETCORR Offset Correction 0x26 16 read-write n 0x0 0xFFFFFFFF OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x1 8 read-write n 0x0 0xFFFFFFFF REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INT1V 1.0V voltage reference 0x0 INTVCC0 1/1.48 VDDANA 0x1 INTVCC1 1/2 VDDANA (only for VDDANA > 2.0V) 0x2 AREFA External reference 0x3 AREFB External reference 0x4 RESULT Result 0x1A 16 read-only n 0x0 0xFFFFFFFF RESULT Result Conversion Value 0 16 read-only SAMPCTRL Sampling Time Control 0x3 8 read-write n 0x0 0xFFFFFFFF SAMPLEN Sampling Time Length 0 6 STATUS Status 0x19 8 read-only n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only SWTRIG Software Trigger 0xC 8 read-write n 0x0 0xFFFFFFFF FLUSH ADC Conversion Flush 0 1 START ADC Start Conversion 1 1 WINCTRL Window Monitor Control 0x8 8 read-write n 0x0 0xFFFFFFFF WINMODE Window Monitor Mode 0 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 Mode 1: RESULT > WINLT 0x1 MODE2 Mode 2: RESULT < WINUT 0x2 MODE3 Mode 3: WINLT < RESULT < WINUT 0x3 MODE4 Mode 4: !(WINLT < RESULT < WINUT) 0x4 WINLT Window Monitor Lower Threshold 0x1C 16 read-write n 0x0 0xFFFFFFFF WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x20 16 read-write n 0x0 0xFFFFFFFF WINUT Window Upper Threshold 0 16 DAC Digital Analog Converter DAC 0x42004800 0x0 0x10 registers n DAC 25 CTRLA Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0xFFFFFFFF BDWP Bypass DATABUF Write Protection 4 1 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0x0 AVCC AVCC 0x1 VREFP External reference 0x2 VPD Voltage Pump Disable 3 1 DATA Data 0x8 16 read-write n 0x0 0xFFFFFFFF DATA Data value to be converted 0 16 DATABUF Data Buffer 0xC 16 read-write n 0x0 0xFFFFFFFF DATABUF Data Buffer 0 16 EVCTRL Event Control 0x2 8 read-write n 0x0 0xFFFFFFFF EMPTYEO Data Buffer Empty Event Output 1 1 STARTEI Start Conversion Event Input 0 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0xFFFFFFFF EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 UNDERRUN Underrun Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0xFFFFFFFF EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 UNDERRUN Underrun Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0xFFFFFFFF EMPTY Data Buffer Empty 1 1 SYNCRDY Synchronization Ready 2 1 UNDERRUN Underrun 0 1 STATUS Status 0x7 8 read-only n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy Status 7 1 read-only DMAC Direct Memory Access Controller DMAC 0x41004800 0x0 0x2C registers n DMAC 6 ACTIVE Active Channel and Levels 0x30 32 read-only n 0x0 0xFFFFFFFF ABUSY Active Channel Busy 15 1 read-only BTCNT Active Channel Block Transfer Count 16 16 read-only ID Active Channel ID 8 5 read-only LVLEX0 Level 0 Channel Trigger Request Executing 0 1 read-only LVLEX1 Level 1 Channel Trigger Request Executing 1 1 read-only LVLEX2 Level 2 Channel Trigger Request Executing 2 1 read-only LVLEX3 Level 3 Channel Trigger Request Executing 3 1 read-only BASEADDR Descriptor Memory Section Base Address 0x34 32 read-write n 0x0 0xFFFFFFFF BASEADDR Descriptor Memory Base Address 0 32 BUSYCH Busy Channels 0x28 32 read-only n 0x0 0xFFFFFFFF BUSYCH0 Busy Channel 0 0 1 read-only BUSYCH1 Busy Channel 1 1 1 read-only BUSYCH10 Busy Channel 10 10 1 read-only BUSYCH11 Busy Channel 11 11 1 read-only BUSYCH2 Busy Channel 2 2 1 read-only BUSYCH3 Busy Channel 3 3 1 read-only BUSYCH4 Busy Channel 4 4 1 read-only BUSYCH5 Busy Channel 5 5 1 read-only BUSYCH6 Busy Channel 6 6 1 read-only BUSYCH7 Busy Channel 7 7 1 read-only BUSYCH8 Busy Channel 8 8 1 read-only BUSYCH9 Busy Channel 9 9 1 read-only CHCTRLA Channel Control A 0x40 8 read-write n 0x0 0xFFFFFFFF ENABLE Channel Enable 1 1 SWRST Channel Software Reset 0 1 CHCTRLB Channel Control B 0x44 32 read-write n 0x0 0xFFFFFFFF CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 LVLSelect LVL0 Channel Priority Level 0 0x0 LVL1 Channel Priority Level 1 0x1 LVL2 Channel Priority Level 2 0x2 LVL3 Channel Priority Level 3 0x3 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 TRIGSRC Peripheral Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x0 CHID Channel ID 0x3F 8 read-write n 0x0 0xFFFFFFFF ID Channel ID 0 4 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 read-write n 0x0 0xFFFFFFFF SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Transfer Complete Interrupt Enable 1 1 TERR Transfer Error Interrupt Enable 0 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 read-write n 0x0 0xFFFFFFFF SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Transfer Complete Interrupt Enable 1 1 TERR Transfer Error Interrupt Enable 0 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 read-write n 0x0 0xFFFFFFFF SUSP Channel Suspend 2 1 TCMPL Transfer Complete 1 1 TERR Transfer Error 0 1 CHSTATUS Channel Status 0x4F 8 read-only n 0x0 0xFFFFFFFF BUSY Channel Busy 1 1 read-only FERR Fetch Error 2 1 read-only PEND Channel Pending 0 1 read-only CRCCHKSUM CRC Checksum 0x8 32 read-write n 0x0 0xFFFFFFFF CRCCHKSUM CRC Checksum 0 32 CRCCTRL CRC Control 0x2 16 read-write n 0x0 0xFFFFFFFF CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE Byte bus access 0x0 HWORD Half-word bus access 0x1 WORD Word bus access 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x0 IO I/O interface 0x1 CRCDATAIN CRC Data Input 0x4 32 read-write n 0x0 0xFFFFFFFF CRCDATAIN CRC Data Input 0 32 CRCSTATUS CRC Status 0xC 8 read-write n 0x0 0xFFFFFFFF CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 read-only CTRL Control 0x0 16 read-write n 0x0 0xFFFFFFFF CRCENABLE CRC Enable 2 1 DMAENABLE DMA Enable 1 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 SWRST Software Reset 0 1 DBGCTRL Debug Control 0xD 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run 0 1 INTPEND Interrupt Pending 0x20 16 read-write n 0x0 0xFFFFFFFF BUSY Busy 14 1 read-only FERR Fetch Error 13 1 read-only ID Channel ID 0 4 PEND Pending 15 1 read-only SUSP Channel Suspend 10 1 TCMPL Transfer Complete 9 1 TERR Transfer Error 8 1 INTSTATUS Interrupt Status 0x24 32 read-only n 0x0 0xFFFFFFFF CHINT0 Channel 0 Pending Interrupt 0 1 read-only CHINT1 Channel 1 Pending Interrupt 1 1 read-only CHINT10 Channel 10 Pending Interrupt 10 1 read-only CHINT11 Channel 11 Pending Interrupt 11 1 read-only CHINT2 Channel 2 Pending Interrupt 2 1 read-only CHINT3 Channel 3 Pending Interrupt 3 1 read-only CHINT4 Channel 4 Pending Interrupt 4 1 read-only CHINT5 Channel 5 Pending Interrupt 5 1 read-only CHINT6 Channel 6 Pending Interrupt 6 1 read-only CHINT7 Channel 7 Pending Interrupt 7 1 read-only CHINT8 Channel 8 Pending Interrupt 8 1 read-only CHINT9 Channel 9 Pending Interrupt 9 1 read-only PENDCH Pending Channels 0x2C 32 read-only n 0x0 0xFFFFFFFF PENDCH0 Pending Channel 0 0 1 read-only PENDCH1 Pending Channel 1 1 1 read-only PENDCH10 Pending Channel 10 10 1 read-only PENDCH11 Pending Channel 11 11 1 read-only PENDCH2 Pending Channel 2 2 1 read-only PENDCH3 Pending Channel 3 3 1 read-only PENDCH4 Pending Channel 4 4 1 read-only PENDCH5 Pending Channel 5 5 1 read-only PENDCH6 Pending Channel 6 6 1 read-only PENDCH7 Pending Channel 7 7 1 read-only PENDCH8 Pending Channel 8 8 1 read-only PENDCH9 Pending Channel 9 9 1 read-only PRICTRL0 Priority Control 0 0x14 32 read-write n 0x0 0xFFFFFFFF LVLPRI0 Level 0 Channel Priority Number 0 4 LVLPRI1 Level 1 Channel Priority Number 8 4 LVLPRI2 Level 2 Channel Priority Number 16 4 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 QOSCTRL QOS Control 0xE 8 read-write n 0x15 0xFFFFFFFF DQOS Data Transfer Quality of Service 4 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 FQOS Fetch Quality of Service 2 2 FQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 WRBQOS Write-Back Quality of Service 0 2 WRBQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 SWTRIGCTRL Software Trigger Control 0x10 32 read-write n 0x0 0xFFFFFFFF SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 WRBADDR Write-Back Memory Section Base Address 0x38 32 read-write n 0x0 0xFFFFFFFF WRBADDR Write-Back Memory Base Address 0 32 DSU Device Service Unit DSU 0x41002000 0x0 0x2000 registers n ADDR Address 0x4 32 read-write n 0x0 0xFFFFFFFF ADDR Address 2 30 CID0 Component Identification 0 0x1FF0 32 read-only n 0xD 0xFFFFFFFF PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only n 0x10 0xFFFFFFFF CCLASS Component Class 4 4 read-only PREAMBLE Preamble 0 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only n 0x5 0xFFFFFFFF PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only n 0xB1 0xFFFFFFFF PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0 8 write-only n 0x0 0xFFFFFFFF CE Chip Erase 4 1 write-only CRC 32-bit Cyclic Redundancy Check 2 1 write-only MBIST Memory Built-In Self-Test 3 1 write-only SWRST Software Reset 0 1 write-only DATA Data 0xC 32 read-write n 0x0 0xFFFFFFFF DATA Data 0 32 DCC0 Debug Communication Channel n 0x20 32 read-write n 0x0 0xFFFFFFFF DATA Data 0 32 DCC1 Debug Communication Channel n 0x34 32 read-write n 0x0 0xFFFFFFFF DATA Data 0 32 DID Device Identification 0x18 32 read-only n 0x10011563 0xFFFFFFFF DEVSEL Device Select 0 8 read-only DIE Die Identification 12 4 read-only FAMILY Product Family 23 5 read-only PROCESSOR Processor 28 4 read-only REVISION Revision 8 4 read-only SERIES Product Series 16 6 read-only END CoreSight ROM Table End 0x1008 32 read-only n 0x0 0xFFFFFFFF END End Marker 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only n 0x9F0FC002 0xFFFFFFFF ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only n 0x3002 0xFFFFFFFF LENGTH Length 0x8 32 read-write n 0x0 0xFFFFFFFF LENGTH Length 2 30 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only n 0x0 0xFFFFFFFF SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only n 0xD0 0xFFFFFFFF PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only n 0xFC 0xFFFFFFFF JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PARTNBH Part Number High 0 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only n 0x9 0xFFFFFFFF JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only n 0x0 0xFFFFFFFF CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only PID4 Peripheral Identification 4 0x1FD0 32 read-only n 0x0 0xFFFFFFFF FKBC 4KB Count 4 4 read-only JEPCC JEP-106 Continuation Code 0 4 STATUSA Status A 0x1 8 read-write n 0x0 0xFFFFFFFF BERR Bus Error 2 1 CRSTEXT CPU Reset Phase Extension 1 1 DONE Done 0 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only n 0x10 0xFFFFFFFF DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 PROT Protected 0 1 EIC External Interrupt Controller EIC 0x40001800 0x0 0x40 registers n EIC 4 CONFIG0 Configuration n 0x30 32 read-write n 0x0 0xFFFFFFFF FILTEN0 Filter 0 Enable 3 1 FILTEN1 Filter 1 Enable 7 1 FILTEN2 Filter 2 Enable 11 1 FILTEN3 Filter 3 Enable 15 1 FILTEN4 Filter 4 Enable 19 1 FILTEN5 Filter 5 Enable 23 1 FILTEN6 Filter 6 Enable 27 1 FILTEN7 Filter 7 Enable 31 1 SENSE0 Input Sense 0 Configuration 0 3 SENSE0Select NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 SENSE1 Input Sense 1 Configuration 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense 2 Configuration 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense 3 Configuration 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense 4 Configuration 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense 5 Configuration 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense 6 Configuration 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense 7 Configuration 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CONFIG1 Configuration n 0x4C 32 read-write n 0x0 0xFFFFFFFF FILTEN0 Filter 0 Enable 3 1 FILTEN1 Filter 1 Enable 7 1 FILTEN2 Filter 2 Enable 11 1 FILTEN3 Filter 3 Enable 15 1 FILTEN4 Filter 4 Enable 19 1 FILTEN5 Filter 5 Enable 23 1 FILTEN6 Filter 6 Enable 27 1 FILTEN7 Filter 7 Enable 31 1 SENSE0 Input Sense 0 Configuration 0 3 SENSE0Select NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 SENSE1 Input Sense 1 Configuration 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense 2 Configuration 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense 3 Configuration 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense 4 Configuration 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense 5 Configuration 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense 6 Configuration 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense 7 Configuration 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CTRL Control 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 SWRST Software Reset 0 1 EVCTRL Event Control 0x4 32 read-write n 0x0 0xFFFFFFFF EXTINTEO0 External Interrupt 0 Event Output Enable 0 1 EXTINTEO1 External Interrupt 1 Event Output Enable 1 1 EXTINTEO10 External Interrupt 10 Event Output Enable 10 1 EXTINTEO11 External Interrupt 11 Event Output Enable 11 1 EXTINTEO12 External Interrupt 12 Event Output Enable 12 1 EXTINTEO13 External Interrupt 13 Event Output Enable 13 1 EXTINTEO14 External Interrupt 14 Event Output Enable 14 1 EXTINTEO15 External Interrupt 15 Event Output Enable 15 1 EXTINTEO2 External Interrupt 2 Event Output Enable 2 1 EXTINTEO3 External Interrupt 3 Event Output Enable 3 1 EXTINTEO4 External Interrupt 4 Event Output Enable 4 1 EXTINTEO5 External Interrupt 5 Event Output Enable 5 1 EXTINTEO6 External Interrupt 6 Event Output Enable 6 1 EXTINTEO7 External Interrupt 7 Event Output Enable 7 1 EXTINTEO8 External Interrupt 8 Event Output Enable 8 1 EXTINTEO9 External Interrupt 9 Event Output Enable 9 1 INTENCLR Interrupt Enable Clear 0x8 32 read-write n 0x0 0xFFFFFFFF EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 INTENSET Interrupt Enable Set 0xC 32 read-write n 0x0 0xFFFFFFFF EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 INTFLAG Interrupt Flag Status and Clear 0x10 32 read-write n 0x0 0xFFFFFFFF EXTINT0 External Interrupt 0 0 1 EXTINT1 External Interrupt 1 1 1 EXTINT10 External Interrupt 10 10 1 EXTINT11 External Interrupt 11 11 1 EXTINT12 External Interrupt 12 12 1 EXTINT13 External Interrupt 13 13 1 EXTINT14 External Interrupt 14 14 1 EXTINT15 External Interrupt 15 15 1 EXTINT2 External Interrupt 2 2 1 EXTINT3 External Interrupt 3 3 1 EXTINT4 External Interrupt 4 4 1 EXTINT5 External Interrupt 5 5 1 EXTINT6 External Interrupt 6 6 1 EXTINT7 External Interrupt 7 7 1 EXTINT8 External Interrupt 8 8 1 EXTINT9 External Interrupt 9 9 1 NMICTRL Non-Maskable Interrupt Control 0x2 8 read-write n 0x0 0xFFFFFFFF NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMISENSE Non-Maskable Interrupt Sense 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x3 8 read-write n 0x0 0xFFFFFFFF NMI Non-Maskable Interrupt 0 1 STATUS Status 0x1 8 read-only n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only WAKEUP Wake-Up Enable 0x14 32 read-write n 0x0 0xFFFFFFFF WAKEUPEN0 External Interrupt 0 Wake-up Enable 0 1 WAKEUPEN1 External Interrupt 1 Wake-up Enable 1 1 WAKEUPEN10 External Interrupt 10 Wake-up Enable 10 1 WAKEUPEN11 External Interrupt 11 Wake-up Enable 11 1 WAKEUPEN12 External Interrupt 12 Wake-up Enable 12 1 WAKEUPEN13 External Interrupt 13 Wake-up Enable 13 1 WAKEUPEN14 External Interrupt 14 Wake-up Enable 14 1 WAKEUPEN15 External Interrupt 15 Wake-up Enable 15 1 WAKEUPEN2 External Interrupt 2 Wake-up Enable 2 1 WAKEUPEN3 External Interrupt 3 Wake-up Enable 3 1 WAKEUPEN4 External Interrupt 4 Wake-up Enable 4 1 WAKEUPEN5 External Interrupt 5 Wake-up Enable 5 1 WAKEUPEN6 External Interrupt 6 Wake-up Enable 6 1 WAKEUPEN7 External Interrupt 7 Wake-up Enable 7 1 WAKEUPEN8 External Interrupt 8 Wake-up Enable 8 1 WAKEUPEN9 External Interrupt 9 Wake-up Enable 9 1 EVSYS Event System Interface EVSYS 0x42000400 0x0 0x2C registers n EVSYS 8 CHANNEL Channel 0x4 32 read-write n 0x0 0xFFFFFFFF CHANNEL Channel Selection 0 4 EDGSEL Edge Detection Selection 26 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 16 7 PATH Path Selection 24 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 SWEVT Software Event 8 1 CHSTATUS Channel Status 0xC 32 read-only n 0xF00FF 0xFFFFFFFF CHBUSY0 Channel 0 Busy 8 1 read-only CHBUSY1 Channel 1 Busy 9 1 read-only CHBUSY10 Channel 10 Busy 26 1 read-only CHBUSY11 Channel 11 Busy 27 1 read-only CHBUSY2 Channel 2 Busy 10 1 read-only CHBUSY3 Channel 3 Busy 11 1 read-only CHBUSY4 Channel 4 Busy 12 1 read-only CHBUSY5 Channel 5 Busy 13 1 read-only CHBUSY6 Channel 6 Busy 14 1 read-only CHBUSY7 Channel 7 Busy 15 1 read-only CHBUSY8 Channel 8 Busy 24 1 read-only CHBUSY9 Channel 9 Busy 25 1 read-only USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY10 Channel 10 User Ready 18 1 read-only USRRDY11 Channel 11 User Ready 19 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only USRRDY8 Channel 8 User Ready 16 1 read-only USRRDY9 Channel 9 User Ready 17 1 read-only CTRL Control 0x0 8 write-only n 0x0 0xFFFFFFFF GCLKREQ Generic Clock Requests 4 1 SWRST Software Reset 0 1 write-only INTENCLR Interrupt Enable Clear 0x10 32 read-write n 0x0 0xFFFFFFFF EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 18 1 OVR11 Channel 11 Overrun Interrupt Enable 19 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 16 1 OVR9 Channel 9 Overrun Interrupt Enable 17 1 INTENSET Interrupt Enable Set 0x14 32 read-write n 0x0 0xFFFFFFFF EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 18 1 OVR11 Channel 11 Overrun Interrupt Enable 19 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 16 1 OVR9 Channel 9 Overrun Interrupt Enable 17 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 read-write n 0x0 0xFFFFFFFF EVD0 Channel 0 Event Detection 8 1 EVD1 Channel 1 Event Detection 9 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 EVD2 Channel 2 Event Detection 10 1 EVD3 Channel 3 Event Detection 11 1 EVD4 Channel 4 Event Detection 12 1 EVD5 Channel 5 Event Detection 13 1 EVD6 Channel 6 Event Detection 14 1 EVD7 Channel 7 Event Detection 15 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR10 Channel 10 Overrun 18 1 OVR11 Channel 11 Overrun 19 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 OVR8 Channel 8 Overrun 16 1 OVR9 Channel 9 Overrun 17 1 USER User Multiplexer 0x8 16 read-write n 0x0 0xFFFFFFFF CHANNEL Channel Event Selection 8 5 CHANNELSelect 0 No Channel Output Selected 0x0 USER User Multiplexer Selection 0 5 GCLK Generic Clock Generator GCLK 0x40000C00 0x0 0x10 registers n CLKCTRL Generic Clock Control 0x2 16 read-write n 0x0 0xFFFFFFFF CLKEN Clock Enable 14 1 GEN Generic Clock Generator 8 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 ID Generic Clock Selection ID 0 6 IDSelect DFLL48 DFLL48 0x0 FDPLL FDPLL 0x1 EVSYS_9 EVSYS_9 0x10 EVSYS_10 EVSYS_10 0x11 EVSYS_11 EVSYS_11 0x12 SERCOMX_SLOW SERCOMX_SLOW 0x13 SERCOM0_CORE SERCOM0_CORE 0x14 SERCOM1_CORE SERCOM1_CORE 0x15 SERCOM2_CORE SERCOM2_CORE 0x16 SERCOM3_CORE SERCOM3_CORE 0x17 SERCOM4_CORE SERCOM4_CORE 0x18 SERCOM5_CORE SERCOM5_CORE 0x19 TCC0_TCC1 TCC0_TCC1 0x1a TCC2_TC3 TCC2_TC3 0x1b TC4_TC5 TC4_TC5 0x1c TC6_TC7 TC6_TC7 0x1d ADC ADC 0x1e AC_DIG AC_DIG 0x1f FDPLL32K FDPLL32K 0x2 AC_ANA AC_ANA 0x20 DAC DAC 0x21 I2S_0 I2S_0 0x23 I2S_1 I2S_1 0x24 WDT WDT 0x3 RTC RTC 0x4 EIC EIC 0x5 USB USB 0x6 EVSYS_0 EVSYS_0 0x7 EVSYS_1 EVSYS_1 0x8 EVSYS_2 EVSYS_2 0x9 EVSYS_3 EVSYS_3 0xa EVSYS_4 EVSYS_4 0xb EVSYS_5 EVSYS_5 0xc EVSYS_6 EVSYS_6 0xd EVSYS_7 EVSYS_7 0xe EVSYS_8 EVSYS_8 0xf WRTLOCK Write Lock 15 1 CTRL Control 0x0 8 read-write n 0x0 0xFFFFFFFF SWRST Software Reset 0 1 GENCTRL Generic Clock Generator Control 0x4 32 read-write n 0x0 0xFFFFFFFF DIVSEL Divide Selection 20 1 GENEN Generic Clock Generator Enable 16 1 ID Generic Clock Generator Selection 0 4 IDC Improve Duty Cycle 17 1 OE Output Enable 19 1 OOV Output Off Value 18 1 RUNSTDBY Run in Standby 21 1 SRC Source Select 8 5 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC8M OSC8M oscillator output 0x6 DFLL48M DFLL48M output 0x7 DPLL96M DPLL96M output 0x8 GENDIV Generic Clock Generator Division 0x8 32 read-write n 0x0 0xFFFFFFFF DIV Division Factor 8 16 ID Generic Clock Generator Selection 0 4 STATUS Status 0x1 8 read-only n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy Status 7 1 read-only HMATRIX HSB Matrix HMATRIXB 0x41007000 0x0 0x400 registers n HMATRIXB_PRAS0 Priority A for Slave 0x100 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS1 Priority A for Slave 0x188 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS10 Priority A for Slave 0x7B8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS11 Priority A for Slave 0x890 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS12 Priority A for Slave 0x970 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS13 Priority A for Slave 0xA58 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS14 Priority A for Slave 0xB48 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS15 Priority A for Slave 0xC40 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS2 Priority A for Slave 0x218 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS3 Priority A for Slave 0x2B0 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS4 Priority A for Slave 0x350 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS5 Priority A for Slave 0x3F8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS6 Priority A for Slave 0x4A8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS7 Priority A for Slave 0x560 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS8 Priority A for Slave 0x620 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRAS9 Priority A for Slave 0x6E8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS0 Priority B for Slave 0x108 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS1 Priority B for Slave 0x194 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS10 Priority B for Slave 0x7E8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS11 Priority B for Slave 0x8C4 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS12 Priority B for Slave 0x9A8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS13 Priority B for Slave 0xA94 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS14 Priority B for Slave 0xB88 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS15 Priority B for Slave 0xC84 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS2 Priority B for Slave 0x228 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS3 Priority B for Slave 0x2C4 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS4 Priority B for Slave 0x368 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS5 Priority B for Slave 0x414 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS6 Priority B for Slave 0x4C8 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS7 Priority B for Slave 0x584 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS8 Priority B for Slave 0x648 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_PRBS9 Priority B for Slave 0x714 32 read-write n 0x0 0xFFFFFFFF HMATRIXB_SFR0 Special Function 0x220 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR1 Special Function 0x334 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR10 Special Function 0xD9C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR11 Special Function 0xED8 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR12 Special Function 0x1018 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR13 Special Function 0x115C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR14 Special Function 0x12A4 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR15 Special Function 0x13F0 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR2 Special Function 0x44C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR3 Special Function 0x568 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR4 Special Function 0x688 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR5 Special Function 0x7AC 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR6 Special Function 0x8D4 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR7 Special Function 0xA00 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR8 Special Function 0xB30 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 HMATRIXB_SFR9 Special Function 0xC64 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 PRAS0 Priority A for Slave 0x80 32 read-write n 0x0 0xFFFFFFFF PRAS1 Priority A for Slave 0x88 32 read-write n 0x0 0xFFFFFFFF PRAS10 Priority A for Slave 0xD0 32 read-write n 0x0 0xFFFFFFFF PRAS11 Priority A for Slave 0xD8 32 read-write n 0x0 0xFFFFFFFF PRAS12 Priority A for Slave 0xE0 32 read-write n 0x0 0xFFFFFFFF PRAS13 Priority A for Slave 0xE8 32 read-write n 0x0 0xFFFFFFFF PRAS14 Priority A for Slave 0xF0 32 read-write n 0x0 0xFFFFFFFF PRAS15 Priority A for Slave 0xF8 32 read-write n 0x0 0xFFFFFFFF PRAS2 Priority A for Slave 0x90 32 read-write n 0x0 0xFFFFFFFF PRAS3 Priority A for Slave 0x98 32 read-write n 0x0 0xFFFFFFFF PRAS4 Priority A for Slave 0xA0 32 read-write n 0x0 0xFFFFFFFF PRAS5 Priority A for Slave 0xA8 32 read-write n 0x0 0xFFFFFFFF PRAS6 Priority A for Slave 0xB0 32 read-write n 0x0 0xFFFFFFFF PRAS7 Priority A for Slave 0xB8 32 read-write n 0x0 0xFFFFFFFF PRAS8 Priority A for Slave 0xC0 32 read-write n 0x0 0xFFFFFFFF PRAS9 Priority A for Slave 0xC8 32 read-write n 0x0 0xFFFFFFFF PRBS0 Priority B for Slave 0x84 32 read-write n 0x0 0xFFFFFFFF PRBS1 Priority B for Slave 0x8C 32 read-write n 0x0 0xFFFFFFFF PRBS10 Priority B for Slave 0xD4 32 read-write n 0x0 0xFFFFFFFF PRBS11 Priority B for Slave 0xDC 32 read-write n 0x0 0xFFFFFFFF PRBS12 Priority B for Slave 0xE4 32 read-write n 0x0 0xFFFFFFFF PRBS13 Priority B for Slave 0xEC 32 read-write n 0x0 0xFFFFFFFF PRBS14 Priority B for Slave 0xF4 32 read-write n 0x0 0xFFFFFFFF PRBS15 Priority B for Slave 0xFC 32 read-write n 0x0 0xFFFFFFFF PRBS2 Priority B for Slave 0x94 32 read-write n 0x0 0xFFFFFFFF PRBS3 Priority B for Slave 0x9C 32 read-write n 0x0 0xFFFFFFFF PRBS4 Priority B for Slave 0xA4 32 read-write n 0x0 0xFFFFFFFF PRBS5 Priority B for Slave 0xAC 32 read-write n 0x0 0xFFFFFFFF PRBS6 Priority B for Slave 0xB4 32 read-write n 0x0 0xFFFFFFFF PRBS7 Priority B for Slave 0xBC 32 read-write n 0x0 0xFFFFFFFF PRBS8 Priority B for Slave 0xC4 32 read-write n 0x0 0xFFFFFFFF PRBS9 Priority B for Slave 0xCC 32 read-write n 0x0 0xFFFFFFFF SFR0 Special Function 0x110 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR1 Special Function 0x114 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR10 Special Function 0x138 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR11 Special Function 0x13C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR12 Special Function 0x140 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR13 Special Function 0x144 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR14 Special Function 0x148 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR15 Special Function 0x14C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR2 Special Function 0x118 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR3 Special Function 0x11C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR4 Special Function 0x120 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR5 Special Function 0x124 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR6 Special Function 0x128 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR7 Special Function 0x12C 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR8 Special Function 0x130 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 SFR9 Special Function 0x134 32 read-write n 0x0 0xFFFFFFFF SFR Special Function Register 0 32 I2S Inter-IC Sound Interface I2S 0x42005000 0x0 0x40 registers n I2S 27 CLKCTRL0 Clock Unit n Control 0x8 32 read-write n 0x0 0xFFFFFFFF BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSINV Frame Sync Invert 11 1 FSOUTINV Frame Sync Output Invert 29 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 MCKDIV Master Clock Division Factor 19 5 MCKEN Master Clock Enable 18 1 MCKOUTDIV Master Clock Output Division Factor 24 5 MCKOUTINV Master Clock Output Invert 31 1 MCKSEL Master Clock Select 16 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 30 1 SCKSEL Serial Clock Select 12 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 CLKCTRL1 Clock Unit n Control 0x10 32 read-write n 0x0 0xFFFFFFFF BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSINV Frame Sync Invert 11 1 FSOUTINV Frame Sync Output Invert 29 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 MCKDIV Master Clock Division Factor 19 5 MCKEN Master Clock Enable 18 1 MCKOUTDIV Master Clock Output Division Factor 24 5 MCKOUTINV Master Clock Output Invert 31 1 MCKSEL Master Clock Select 16 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 30 1 SCKSEL Serial Clock Select 12 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 CTRLA Control A 0x0 8 read-write n 0x0 0xFFFFFFFF CKEN0 Clock Unit 0 Enable 2 1 CKEN1 Clock Unit 1 Enable 3 1 ENABLE Enable 1 1 SEREN0 Serializer 0 Enable 4 1 SEREN1 Serializer 1 Enable 5 1 SWRST Software Reset 0 1 DATA0 Data n 0x60 32 read-write n 0x0 0xFFFFFFFF DATA Sample Data 0 32 DATA1 Data n 0x94 32 read-write n 0x0 0xFFFFFFFF DATA Sample Data 0 32 INTENCLR Interrupt Enable Clear 0xC 16 read-write n 0x0 0xFFFFFFFF RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTENSET Interrupt Enable Set 0x10 16 read-write n 0x0 0xFFFFFFFF RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTFLAG Interrupt Flag Status and Clear 0x14 16 read-write n 0x0 0xFFFFFFFF RXOR0 Receive Overrun 0 4 1 RXOR1 Receive Overrun 1 5 1 RXRDY0 Receive Ready 0 0 1 RXRDY1 Receive Ready 1 1 1 TXRDY0 Transmit Ready 0 8 1 TXRDY1 Transmit Ready 1 9 1 TXUR0 Transmit Underrun 0 12 1 TXUR1 Transmit Underrun 1 13 1 SERCTRL0 Serializer n Control 0x40 32 read-write n 0x0 0xFFFFFFFF BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x0 LSBIT Transfer Data Least Significant Bit (LSB) first 0x1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0x0 CLK1 Use Clock Unit 1 0x1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0x0 ONE Extend with ones 0x1 MSBIT Extend with Most Significant Bit 0x2 LSBIT Extend with Least Significant Bit 0x3 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 RXLOOP Loop-back Test Mode 26 1 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0x0 TX Transmit 0x1 PDM2 Receive one PDM data on each serial clock edge 0x2 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0x0 LEFT Data is left adjusted in slot 0x1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 TXDEFAULT Line Default Line when Slot Disabled 2 2 TXDEFAULTSelect ZERO Output Default Value is 0 0x0 ONE Output Default Value is 1 0x1 HIZ Output Default Value is high impedance 0x3 TXSAME Transmit Data when Underrun 4 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0x0 LEFT Data is left adjusted in word 0x1 SERCTRL1 Serializer n Control 0x64 32 read-write n 0x0 0xFFFFFFFF BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x0 LSBIT Transfer Data Least Significant Bit (LSB) first 0x1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0x0 CLK1 Use Clock Unit 1 0x1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0x0 ONE Extend with ones 0x1 MSBIT Extend with Most Significant Bit 0x2 LSBIT Extend with Least Significant Bit 0x3 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 RXLOOP Loop-back Test Mode 26 1 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0x0 TX Transmit 0x1 PDM2 Receive one PDM data on each serial clock edge 0x2 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0x0 LEFT Data is left adjusted in slot 0x1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 TXDEFAULT Line Default Line when Slot Disabled 2 2 TXDEFAULTSelect ZERO Output Default Value is 0 0x0 ONE Output Default Value is 1 0x1 HIZ Output Default Value is high impedance 0x3 TXSAME Transmit Data when Underrun 4 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0x0 LEFT Data is left adjusted in word 0x1 SYNCBUSY Synchronization Status 0x18 16 read-only n 0x0 0xFFFFFFFF CKEN0 Clock Unit 0 Enable Synchronization Status 2 1 CKEN1 Clock Unit 1 Enable Synchronization Status 3 1 DATA0 Data 0 Synchronization Status 8 1 DATA1 Data 1 Synchronization Status 9 1 ENABLE Enable Synchronization Status 1 1 SEREN0 Serializer 0 Enable Synchronization Status 4 1 SEREN1 Serializer 1 Enable Synchronization Status 5 1 SWRST Software Reset Synchronization Status 0 1 MTB Cortex-M0+ Micro-Trace Buffer MTB 0x41006000 0x0 0x1000 registers n AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only n 0x0 0xFFFFFFFF BASE MTB Base 0xC 32 read-only n 0x0 0xFFFFFFFF CID0 CoreSight 0xFF0 32 read-only n 0x0 0xFFFFFFFF CID1 CoreSight 0xFF4 32 read-only n 0x0 0xFFFFFFFF CID2 CoreSight 0xFF8 32 read-only n 0x0 0xFFFFFFFF CID3 CoreSight 0xFFC 32 read-only n 0x0 0xFFFFFFFF CLAIMCLR MTB Claim Clear 0xFA4 32 read-write n 0x0 0xFFFFFFFF CLAIMSET MTB Claim Set 0xFA0 32 read-write n 0x0 0xFFFFFFFF DEVARCH MTB Device Architecture 0xFBC 32 read-only n 0x0 0xFFFFFFFF DEVID MTB Device Configuration 0xFC8 32 read-only n 0x0 0xFFFFFFFF DEVTYPE MTB Device Type 0xFCC 32 read-only n 0x0 0xFFFFFFFF FLOW MTB Flow 0x8 32 read-write n 0x0 0xFFFFFFFF AUTOHALT Auto Halt Request 1 1 AUTOSTOP Auto Stop Tracing 0 1 WATERMARK Watermark value 3 29 ITCTRL MTB Integration Mode Control 0xF00 32 read-write n 0x0 0xFFFFFFFF LOCKACCESS MTB Lock Access 0xFB0 32 read-write n 0x0 0xFFFFFFFF LOCKSTATUS MTB Lock Status 0xFB4 32 read-only n 0x0 0xFFFFFFFF MASTER MTB Master 0x4 32 read-write n 0x0 0xFFFFFFFF EN Main Trace Enable 31 1 HALTREQ Halt Request 9 1 MASK Maximum Value of the Trace Buffer in SRAM 0 5 RAMPRIV SRAM Privilege 8 1 SFRWPRIV Special Function Register Write Privilege 7 1 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 PID0 CoreSight 0xFE0 32 read-only n 0x0 0xFFFFFFFF PID1 CoreSight 0xFE4 32 read-only n 0x0 0xFFFFFFFF PID2 CoreSight 0xFE8 32 read-only n 0x0 0xFFFFFFFF PID3 CoreSight 0xFEC 32 read-only n 0x0 0xFFFFFFFF PID4 CoreSight 0xFD0 32 read-only n 0x0 0xFFFFFFFF PID5 CoreSight 0xFD4 32 read-only n 0x0 0xFFFFFFFF PID6 CoreSight 0xFD8 32 read-only n 0x0 0xFFFFFFFF PID7 CoreSight 0xFDC 32 read-only n 0x0 0xFFFFFFFF POSITION MTB Position 0x0 32 read-write n 0x0 0xFFFFFFFF POINTER Trace Packet Location Pointer 3 29 WRAP Pointer Value Wraps 2 1 NVMCTRL Non-Volatile Memory Controller NVMCTRL 0x41004000 0x0 0x2C registers n NVMCTRL 5 ADDR Address 0x1C 32 read-write n 0x0 0xFFFFFFFF ADDR NVM Address 0 22 CTRLA Control A 0x0 16 read-write n 0x0 0xFFFFFFFF CMD Command 0 7 CMDSelect RWWEEER RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. 0x1a RWWEEWP RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x1c ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x4 32 read-write n 0x0 0xFFFFFFFF CACHEDIS Cache Disable 18 1 MANW Manual Write 7 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x10 8 read-write n 0x0 0xFFFFFFFF ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 read-write n 0x0 0xFFFFFFFF ERROR Error 1 1 READY NVM Ready 0 1 LOCK Lock Section 0x20 16 read-write n 0x0 0xFFFFFFFF LOCK Region Lock Bits 0 16 read-only PARAM NVM Parameter 0x8 32 read-write n 0x0 0xFFFFFFFF NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 RWWEEP RWW EEPROM Pages 20 12 read-only STATUS Status 0x18 16 read-write n 0x0 0xFFFFFFFF LOAD NVM Page Buffer Active Loading 1 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 PRM Power Reduction Mode 0 1 read-only PROGE Programming Error Status 2 1 SB Security Bit Status 8 1 read-only PAC0 Peripheral Access Controller 0 PAC 0x40000000 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 PAC1 Peripheral Access Controller 1 PAC 0x41000000 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 PAC2 Peripheral Access Controller 2 PAC 0x42000000 0x0 0x8 registers n PAC_WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 PAC_WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 WPCLR Write Protection Clear 0x0 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 read-write n 0x0 0xFFFFFFFF WP Write Protection Set 1 31 PM Power Manager PM 0x40000400 0x0 0x2C registers n PM 0 AHBMASK AHB Mask 0x14 32 read-write n 0x7F 0xFFFFFFFF DMAC_ DMAC AHB Clock Mask 5 1 DSU_ DSU AHB Clock Mask 3 1 HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 NVMCTRL_ NVMCTRL AHB Clock Mask 4 1 USB_ USB AHB Clock Mask 6 1 APBAMASK APBA Mask 0x18 32 read-write n 0x7F 0xFFFFFFFF EIC_ EIC APB Clock Enable 6 1 GCLK_ GCLK APB Clock Enable 3 1 PAC0_ PAC0 APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 RTC_ RTC APB Clock Enable 5 1 SYSCTRL_ SYSCTRL APB Clock Enable 2 1 WDT_ WDT APB Clock Enable 4 1 APBASEL APBA Clock Select 0x9 8 read-write n 0x0 0xFFFFFFFF APBADIV APBA Prescaler Selection 0 3 APBADIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBBMASK APBB Mask 0x1C 32 read-write n 0x7F 0xFFFFFFFF DMAC_ DMAC APB Clock Enable 4 1 DSU_ DSU APB Clock Enable 1 1 HMATRIX_ HMATRIX APB Clock Enable 6 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 PAC1_ PAC1 APB Clock Enable 0 1 PORT_ PORT APB Clock Enable 3 1 USB_ USB APB Clock Enable 5 1 APBBSEL APBB Clock Select 0xA 8 read-write n 0x0 0xFFFFFFFF APBBDIV APBB Prescaler Selection 0 3 APBBDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBCMASK APBC Mask 0x20 32 read-write n 0x10000 0xFFFFFFFF AC_ AC APB Clock Enable 17 1 ADC_ ADC APB Clock Enable 16 1 DAC_ DAC APB Clock Enable 18 1 EVSYS_ EVSYS APB Clock Enable 1 1 I2S_ I2S APB Clock Enable 20 1 PAC2_ PAC2 APB Clock Enable 0 1 PTC_ PTC APB Clock Enable 19 1 SERCOM0_ SERCOM0 APB Clock Enable 2 1 SERCOM1_ SERCOM1 APB Clock Enable 3 1 SERCOM2_ SERCOM2 APB Clock Enable 4 1 SERCOM3_ SERCOM3 APB Clock Enable 5 1 TC3_ TC3 APB Clock Enable 11 1 TC4_ TC4 APB Clock Enable 12 1 TC5_ TC5 APB Clock Enable 13 1 TCC0_ TCC0 APB Clock Enable 8 1 TCC1_ TCC1 APB Clock Enable 9 1 TCC2_ TCC2 APB Clock Enable 10 1 APBCSEL APBC Clock Select 0xB 8 read-write n 0x0 0xFFFFFFFF APBCDIV APBC Prescaler Selection 0 3 APBCDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CPUSEL CPU Clock Select 0x8 8 read-write n 0x0 0xFFFFFFFF CPUDIV CPU Prescaler Selection 0 3 CPUDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CTRL Control 0x0 8 read-write n 0x0 0xFFFFFFFF EXTCTRL External Reset Controller 0x2 8 read-write n 0x0 0xFFFFFFFF SETDIS External Reset Disable 0 1 INTENCLR Interrupt Enable Clear 0x34 8 read-write n 0x0 0xFFFFFFFF CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x35 8 read-write n 0x0 0xFFFFFFFF CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x36 8 read-write n 0x0 0xFFFFFFFF CKRDY Clock Ready 0 1 RCAUSE Reset Cause 0x38 8 read-only n 0x1 0xFFFFFFFF BOD12 Brown Out 12 Detector Reset 1 1 BOD33 Brown Out 33 Detector Reset 2 1 EXT External Reset 4 1 POR Power On Reset 0 1 SYST System Reset Request 6 1 WDT Watchdog Reset 5 1 SLEEP Sleep Mode 0x1 8 read-write n 0x0 0xFFFFFFFF IDLE Idle Mode Configuration 0 2 IDLESelect CPU The CPU clock domain is stopped 0x0 AHB The CPU and AHB clock domains are stopped 0x1 APB The CPU, AHB and APB clock domains are stopped 0x2 PORT Port Module PORT 0x41004400 0x0 0x200 registers n CTRL0 Control 0x48 32 read-write n 0x0 0xFFFFFFFF SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0x24 32 read-write n 0x0 0xFFFFFFFF SAMPLING Input Sampling Mode 0 32 write-only DIR0 Data Direction 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Port Data Direction 0 32 DIR1 Data Direction 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Port Data Direction 0 32 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0xFFFFFFFF DIRCLR Port Data Direction Clear 0 32 DIRCLR1 Data Direction Clear 0x4 32 read-write n 0x0 0xFFFFFFFF DIRCLR Port Data Direction Clear 0 32 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0xFFFFFFFF DIRSET Port Data Direction Set 0 32 DIRSET1 Data Direction Set 0x8 32 read-write n 0x0 0xFFFFFFFF DIRSET Port Data Direction Set 0 32 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0xFFFFFFFF DIRTGL Port Data Direction Toggle 0 32 DIRTGL1 Data Direction Toggle 0xC 32 read-write n 0x0 0xFFFFFFFF DIRTGL Port Data Direction Toggle 0 32 IN0 Data Input Value 0x40 32 read-only n 0x0 0xFFFFFFFF IN Port Data Input Value 0 32 IN1 Data Input Value 0x20 32 read-only n 0x0 0xFFFFFFFF IN Port Data Input Value 0 32 OUT0 Data Output Value 0x20 32 read-write n 0x0 0xFFFFFFFF OUT Port Data Output Value 0 32 OUT1 Data Output Value 0x10 32 read-write n 0x0 0xFFFFFFFF OUT Port Data Output Value 0 32 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0xFFFFFFFF OUTCLR Port Data Output Value Clear 0 32 OUTCLR1 Data Output Value Clear 0x14 32 read-write n 0x0 0xFFFFFFFF OUTCLR Port Data Output Value Clear 0 32 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0xFFFFFFFF OUTSET Port Data Output Value Set 0 32 OUTSET1 Data Output Value Set 0x18 32 read-write n 0x0 0xFFFFFFFF OUTSET Port Data Output Value Set 0 32 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0xFFFFFFFF OUTTGL Port Data Output Value Toggle 0 32 OUTTGL1 Data Output Value Toggle 0x1C 32 read-write n 0x0 0xFFFFFFFF OUTTGL Port Data Output Value Toggle 0 32 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 WRCONFIG1 Write Configuration 0x28 32 write-only n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 PORT_IOBUS Port Module (IOBUS) PORT 0x60000000 0x0 0x200 registers n CTRL0 Control 0x48 32 read-write n 0x0 0xFFFFFFFF SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0x24 32 read-write n 0x0 0xFFFFFFFF SAMPLING Input Sampling Mode 0 32 write-only DIR0 Data Direction 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Port Data Direction 0 32 DIR1 Data Direction 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Port Data Direction 0 32 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0xFFFFFFFF DIRCLR Port Data Direction Clear 0 32 DIRCLR1 Data Direction Clear 0x4 32 read-write n 0x0 0xFFFFFFFF DIRCLR Port Data Direction Clear 0 32 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0xFFFFFFFF DIRSET Port Data Direction Set 0 32 DIRSET1 Data Direction Set 0x8 32 read-write n 0x0 0xFFFFFFFF DIRSET Port Data Direction Set 0 32 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0xFFFFFFFF DIRTGL Port Data Direction Toggle 0 32 DIRTGL1 Data Direction Toggle 0xC 32 read-write n 0x0 0xFFFFFFFF DIRTGL Port Data Direction Toggle 0 32 IN0 Data Input Value 0x40 32 read-only n 0x0 0xFFFFFFFF IN Port Data Input Value 0 32 IN1 Data Input Value 0x20 32 read-only n 0x0 0xFFFFFFFF IN Port Data Input Value 0 32 OUT0 Data Output Value 0x20 32 read-write n 0x0 0xFFFFFFFF OUT Port Data Output Value 0 32 OUT1 Data Output Value 0x10 32 read-write n 0x0 0xFFFFFFFF OUT Port Data Output Value 0 32 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0xFFFFFFFF OUTCLR Port Data Output Value Clear 0 32 OUTCLR1 Data Output Value Clear 0x14 32 read-write n 0x0 0xFFFFFFFF OUTCLR Port Data Output Value Clear 0 32 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0xFFFFFFFF OUTSET Port Data Output Value Set 0 32 OUTSET1 Data Output Value Set 0x18 32 read-write n 0x0 0xFFFFFFFF OUTSET Port Data Output Value Set 0 32 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0xFFFFFFFF OUTTGL Port Data Output Value Toggle 0 32 OUTTGL1 Data Output Value Toggle 0x1C 32 read-write n 0x0 0xFFFFFFFF OUTTGL Port Data Output Value Toggle 0 32 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0xFFFFFFFF PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 WRCONFIG1 Write Configuration 0x28 32 write-only n 0x0 0xFFFFFFFF DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 RTC Real-Time Counter RTC 0x40001400 0x0 0x40 registers n RTC 3 ALARM1 MODE2 Alarm n Value 0x18 32 read-write n 0x0 0xFFFFFFFF DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 CLOCK MODE2 Clock Value 0x10 32 read-write n 0x0 0xFFFFFFFF DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x0 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 COMP0 MODE1 Compare n Value 0x18 16 read-write n 0x0 0xFFFFFFFF COMP Compare Value 0 16 COMP1 MODE1 Compare n Value 0x1A 16 read-write n 0x0 0xFFFFFFFF COMP Compare Value 0 16 COUNT MODE1 Counter Value 0x10 16 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 16 CTRL MODE2 Control 0x0 16 read-write n 0x0 0xFFFFFFFF CLKREP Clock Representation 6 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only DBGCTRL Debug Control 0xB 8 read-write n 0x0 0xFFFFFFFF DBGRUN Run During Debug 0 1 EVCTRL MODE2 Event Control 0x4 16 read-write n 0x0 0xFFFFFFFF ALARMEO0 Alarm 0 Event Output Enable 8 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 FREQCORR Frequency Correction 0xC 8 read-write n 0x0 0xFFFFFFFF SIGN Correction Sign 7 1 VALUE Correction Value 0 7 INTENCLR MODE2 Interrupt Enable Clear 0x6 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 Interrupt Enable 0 1 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 INTENSET MODE2 Interrupt Enable Set 0x7 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 Interrupt Enable 0 1 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 0 1 CMP0 Compare 0 0 1 CMP1 Compare 1 1 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MASK1 MODE2 Alarm n Mask 0x1C 8 read-write n 0x0 0xFFFFFFFF SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE0 - COMP0 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x30 32 read-write n 0x0 0xFFFFFFFF COMP Compare Value 0 32 MODE0 - COUNT 32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 32 MODE0 - CTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Control 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE0 - DBGCTRL 32-bit Counter with Single 32-bit Compare - - Debug Control 0xB 8 read-write n 0x0 0xFFFFFFFF DBGRUN Run During Debug 0 1 MODE0 - EVCTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Event Control 0x4 16 read-write n 0x0 0xFFFFFFFF CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE0 - FREQCORR 32-bit Counter with Single 32-bit Compare - - Frequency Correction 0xC 8 read-write n 0x0 0xFFFFFFFF SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE0 - INTENCLR 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear 0x6 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE0 - INTENSET 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set 0x7 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE0 - INTFLAG 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 0 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE0 - READREQ 32-bit Counter with Single 32-bit Compare - - Read Request 0x2 16 read-write n 0x10 0xFFFFFFFF ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE0 - STATUS 32-bit Counter with Single 32-bit Compare - - Status 0xA 8 read-write n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only MODE1 - COMP0 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x30 16 read-write n 0x0 0xFFFFFFFF COMP Compare Value 0 16 MODE1 - COMP1 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x4A 16 read-write n 0x0 0xFFFFFFFF COMP Compare Value 0 16 MODE1 - COUNT 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value 0x10 16 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 16 MODE1 - CTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Control 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE1 - DBGCTRL 16-bit Counter with Two 16-bit Compares - - Debug Control 0xB 8 read-write n 0x0 0xFFFFFFFF DBGRUN Run During Debug 0 1 MODE1 - EVCTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Event Control 0x4 16 read-write n 0x0 0xFFFFFFFF CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE1 - FREQCORR 16-bit Counter with Two 16-bit Compares - - Frequency Correction 0xC 8 read-write n 0x0 0xFFFFFFFF SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE1 - INTENCLR 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear 0x6 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE1 - INTENSET 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set 0x7 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE1 - INTFLAG 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0xFFFFFFFF CMP0 Compare 0 0 1 CMP1 Compare 1 1 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE1 - PER 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period 0x14 16 read-write n 0x0 0xFFFFFFFF PER Counter Period 0 16 MODE1 - READREQ 16-bit Counter with Two 16-bit Compares - - Read Request 0x2 16 read-write n 0x10 0xFFFFFFFF ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE1 - STATUS 16-bit Counter with Two 16-bit Compares - - Status 0xA 8 read-write n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only MODE2 - ALARM0 Clock/Calendar with Alarm - - MODE2 Alarm n Value 0x30 32 read-write n 0x0 0xFFFFFFFF DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CLOCK Clock/Calendar with Alarm - - MODE2 Clock Value 0x10 32 read-write n 0x0 0xFFFFFFFF DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x0 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CTRL Clock/Calendar with Alarm - - MODE2 Control 0x0 16 read-write n 0x0 0xFFFFFFFF CLKREP Clock Representation 6 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa SWRST Software Reset 0 1 write-only MODE2 - DBGCTRL Clock/Calendar with Alarm - - Debug Control 0xB 8 read-write n 0x0 0xFFFFFFFF DBGRUN Run During Debug 0 1 MODE2 - EVCTRL Clock/Calendar with Alarm - - MODE2 Event Control 0x4 16 read-write n 0x0 0xFFFFFFFF ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE2 - FREQCORR Clock/Calendar with Alarm - - Frequency Correction 0xC 8 read-write n 0x0 0xFFFFFFFF SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE2 - INTENCLR Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear 0x6 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE2 - INTENSET Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set 0x7 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 Interrupt Enable 0 1 OVF Overflow Interrupt Enable 7 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 MODE2 - INTFLAG Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear 0x8 8 read-write n 0x0 0xFFFFFFFF ALARM0 Alarm 0 0 1 OVF Overflow 7 1 SYNCRDY Synchronization Ready 6 1 MODE2 - MASK0 Clock/Calendar with Alarm - - MODE2 Alarm n Mask 0x38 8 read-write n 0x0 0xFFFFFFFF SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE2 - READREQ Clock/Calendar with Alarm - - Read Request 0x2 16 read-write n 0x10 0xFFFFFFFF ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only MODE2 - STATUS Clock/Calendar with Alarm - - Status 0xA 8 read-write n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only PER MODE1 Counter Period 0x14 16 read-write n 0x0 0xFFFFFFFF PER Counter Period 0 16 READREQ Read Request 0x2 16 read-write n 0x10 0xFFFFFFFF ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only STATUS Status 0xA 8 read-write n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only SERCOM0 Serial Communication Interface 0 SERCOM 0x42000800 0x0 0x40 registers n SERCOM0 9 ADDR SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 CTRLA USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0xFFFFFFFF ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM1 Serial Communication Interface 1 SERCOM 0x42000C00 0x0 0x40 registers n SERCOM1 10 ADDR SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 CTRLA USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0xFFFFFFFF ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM2 Serial Communication Interface 2 SERCOM 0x42001000 0x0 0x40 registers n SERCOM2 11 ADDR SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 CTRLA USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0xFFFFFFFF ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM3 Serial Communication Interface 3 SERCOM 0x42001400 0x0 0x40 registers n SERCOM3 12 ADDR SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 CTRLA USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 CTRLB USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 DATA USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0xFFFFFFFF ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0xFFFFFFFF ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0xFFFFFFFF AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0xFFFFFFFF BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0xFFFFFFFF CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0xFFFFFFFF CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0xFFFFFFFF DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0xFFFFFFFF DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0xFFFFFFFF CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0xFFFFFFFF RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART Status 0x1A 16 read-write n 0x0 0xFFFFFFFF ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only DIR Read/Write Direction 3 1 read-only FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SYNCBUSY USART Synchronization Busy 0x1C 32 read-only n 0x0 0xFFFFFFFF CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SYSCTRL System Control SYSCTRL 0x40000800 0x0 0x2C registers n SYSCTRL 1 BOD33 3.3V Brown-Out Detector (BOD33) Control 0x34 32 read-write n 0x0 0xFFFFFFFF ACTION BOD33 Action 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INTERRUPT The BOD33 generates an interrupt 0x2 CEN Clock Enable 9 1 ENABLE Enable 1 1 HYST Hysteresis 2 1 LEVEL BOD33 Threshold Level 16 6 MODE Operation Mode 8 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1K Divide clock by 1024 0x9 DIV2K Divide clock by 2048 0xa DIV4K Divide clock by 4096 0xb DIV8K Divide clock by 8192 0xc DIV16K Divide clock by 16384 0xd DIV32K Divide clock by 32768 0xe DIV64K Divide clock by 65536 0xf RUNSTDBY Run in Standby 6 1 DFLLCTRL DFLL48M Control 0x24 16 read-write n 0x80 0xFFFFFFFF BPLCKC Bypass Coarse Lock 10 1 CCDIS Chill Cycle Disable 8 1 ENABLE DFLL Enable 1 1 LLAW Lose Lock After Wake 4 1 MODE Operating Mode Selection 2 1 ONDEMAND On Demand Control 7 1 QLDIS Quick Lock Disable 9 1 RUNSTDBY Run in Standby 6 1 STABLE Stable DFLL Frequency 3 1 USBCRM USB Clock Recovery Mode 5 1 WAITLOCK Wait Lock 11 1 DFLLMUL DFLL48M Multiplier 0x2C 32 read-write n 0x0 0xFFFFFFFF CSTEP Coarse Maximum Step 26 6 FSTEP Fine Maximum Step 16 10 MUL DFLL Multiply Factor 0 16 DFLLSYNC DFLL48M Synchronization 0x30 8 read-write n 0x0 0xFFFFFFFF READREQ Read Request 7 1 write-only DFLLVAL DFLL48M Value 0x28 32 read-write n 0x0 0xFFFFFFFF COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 read-only FINE Fine Value 0 10 DPLLCTRLA DPLL Control A 0x44 8 read-write n 0x80 0xFFFFFFFF ENABLE DPLL Enable 1 1 ONDEMAND On Demand Clock Activation 7 1 RUNSTDBY Run in Standby 6 1 DPLLCTRLB DPLL Control B 0x4C 32 read-write n 0x0 0xFFFFFFFF DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 2 FILTERSelect DEFAULT Default filter mode 0x0 LBFILT Low bandwidth filter 0x1 HBFILT High bandwidth filter 0x2 HDFILT High damping filter 0x3 LBYPASS Lock Bypass 12 1 LPEN Low-Power Enable 2 1 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out 0x0 8MS Time-out if no lock within 8 ms 0x4 9MS Time-out if no lock within 9 ms 0x5 10MS Time-out if no lock within 10 ms 0x6 11MS Time-out if no lock within 11 ms 0x7 REFCLK Reference Clock Selection 4 2 REFCLKSelect REF0 CLK_DPLL_REF0 clock reference 0x0 REF1 CLK_DPLL_REF1 clock reference 0x1 GCLK GCLK_DPLL clock reference 0x2 WUF Wake Up Fast 3 1 DPLLRATIO DPLL Ratio Control 0x48 32 read-write n 0x0 0xFFFFFFFF LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLSTATUS DPLL Status 0x50 8 read-only n 0x0 0xFFFFFFFF CLKRDY Output Clock Ready 1 1 read-only DIV Divider Enable 3 1 read-only ENABLE DPLL Enable 2 1 read-only LOCK DPLL Lock Status 0 1 read-only INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0xFFFFFFFF B33SRDY BOD33 Synchronization Ready Interrupt Enable 11 1 BOD33DET BOD33 Detection Interrupt Enable 10 1 BOD33RDY BOD33 Ready Interrupt Enable 9 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 7 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 6 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 5 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 8 1 DFLLRDY DFLL Ready Interrupt Enable 4 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 16 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 15 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 17 1 OSC32KRDY OSC32K Ready Interrupt Enable 2 1 OSC8MRDY OSC8M Ready Interrupt Enable 3 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 1 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0xFFFFFFFF B33SRDY BOD33 Synchronization Ready Interrupt Enable 11 1 BOD33DET BOD33 Detection Interrupt Enable 10 1 BOD33RDY BOD33 Ready Interrupt Enable 9 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 7 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 6 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 5 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 8 1 DFLLRDY DFLL Ready Interrupt Enable 4 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 16 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 15 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 17 1 OSC32KRDY OSC32K Ready Interrupt Enable 2 1 OSC8MRDY OSC8M Ready Interrupt Enable 3 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 1 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0xFFFFFFFF B33SRDY BOD33 Synchronization Ready 11 1 BOD33DET BOD33 Detection 10 1 BOD33RDY BOD33 Ready 9 1 DFLLLCKC DFLL Lock Coarse 7 1 DFLLLCKF DFLL Lock Fine 6 1 DFLLOOB DFLL Out Of Bounds 5 1 DFLLRCS DFLL Reference Clock Stopped 8 1 DFLLRDY DFLL Ready 4 1 DPLLLCKF DPLL Lock Fall 16 1 DPLLLCKR DPLL Lock Rise 15 1 DPLLLTO DPLL Lock Timeout 17 1 OSC32KRDY OSC32K Ready 2 1 OSC8MRDY OSC8M Ready 3 1 XOSC32KRDY XOSC32K Ready 1 1 XOSCRDY XOSC Ready 0 1 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 read-write n 0x3F0080 0xFFFFFFFF CALIB Oscillator Calibration 16 7 EN1K 1kHz Output Enable 3 1 EN32K 32kHz Output Enable 2 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 OSC8M 8MHz Internal Oscillator (OSC8M) Control 0x20 32 read-write n 0x87070382 0xFFFFFFFF CALIB Oscillator Calibration 16 12 ENABLE Oscillator Enable 1 1 FRANGE Oscillator Frequency Range 30 2 FRANGESelect 0 4 to 6MHz 0x0 1 6 to 8MHz 0x1 2 8 to 11MHz 0x2 3 11 to 15MHz 0x3 ONDEMAND On Demand Control 7 1 PRESC Oscillator Prescaler 8 2 PRESCSelect 0 1 0x0 1 2 0x1 2 4 0x2 3 8 0x3 RUNSTDBY Run in Standby 6 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 8 read-write n 0x1F 0xFFFFFFFF CALIB Oscillator Calibration 0 5 WRTLOCK Write Lock 7 1 PCLKSR Power and Clocks Status 0xC 32 read-only n 0x0 0xFFFFFFFF B33SRDY BOD33 Synchronization Ready 11 1 read-only BOD33DET BOD33 Detection 10 1 read-only BOD33RDY BOD33 Ready 9 1 read-only DFLLLCKC DFLL Lock Coarse 7 1 read-only DFLLLCKF DFLL Lock Fine 6 1 read-only DFLLOOB DFLL Out Of Bounds 5 1 read-only DFLLRCS DFLL Reference Clock Stopped 8 1 read-only DFLLRDY DFLL Ready 4 1 read-only DPLLLCKF DPLL Lock Fall 16 1 read-only DPLLLCKR DPLL Lock Rise 15 1 read-only DPLLLTO DPLL Lock Timeout 17 1 read-only OSC32KRDY OSC32K Ready 2 1 read-only OSC8MRDY OSC8M Ready 3 1 read-only XOSC32KRDY XOSC32K Ready 1 1 read-only XOSCRDY XOSC Ready 0 1 read-only VREF Voltage References System (VREF) Control 0x40 32 read-write n 0x0 0xFFFFFFFF BGOUTEN Bandgap Output Enable 2 1 CALIB Bandgap Voltage Generator Calibration 16 11 TSEN Temperature Sensor Enable 1 1 VREG Voltage Regulator System (VREG) Control 0x3C 16 read-write n 0x0 0xFFFFFFFF FORCELDO Force LDO Voltage Regulator 13 1 RUNSTDBY Run in Standby 6 1 XOSC External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 read-write n 0x80 0xFFFFFFFF AMPGC Automatic Amplitude Gain Control 11 1 ENABLE Oscillator Enable 1 1 GAIN Oscillator Gain 8 3 GAINSelect 0 2MHz 0x0 1 4MHz 0x1 2 8MHz 0x2 3 16MHz 0x3 4 30MHz 0x4 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 12 4 XTALEN Crystal Oscillator Enable 2 1 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 read-write n 0x80 0xFFFFFFFF AAMPEN Automatic Amplitude Control Enable 5 1 EN1K 1kHz Output Enable 4 1 EN32K 32kHz Output Enable 3 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 XTALEN Crystal Oscillator Enable 2 1 TC3 Basic Timer Counter 3 TC 0x42002C00 0x0 0x40 registers n TC3 18 CC0 COUNT32 Compare/Capture 0x18 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 CC1 COUNT32 Compare/Capture 0x1C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 COUNT COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC4 Basic Timer Counter 4 TC 0x42003000 0x0 0x40 registers n TC4 19 CC0 COUNT32 Compare/Capture 0x18 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 CC1 COUNT32 Compare/Capture 0x1C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 COUNT COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC5 Basic Timer Counter 5 TC 0x42003400 0x0 0x40 registers n TC5 20 CC0 COUNT32 Compare/Capture 0x18 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 CC1 COUNT32 Compare/Capture 0x1C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 COUNT COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 CTRLA Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 CTRLBCLR Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CTRLC Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 DBGCTRL Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 PER COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 READREQ Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare/Capture 0x30 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare/Capture 0x4A 16 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Counter Value 0x10 16 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT16 - CTRLC 16-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT16 - READREQ 16-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare/Capture 0x30 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare/Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Counter Value 0x10 32 read-write n 0x0 0xFFFFFFFF COUNT Count Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT32 - CTRLC 32-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT32 - READREQ 32-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare/Capture 0x30 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare/Capture 0x49 8 read-write n 0x0 0xFFFFFFFF CC Compare/Capture Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Counter Value 0x10 8 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 16 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 write-only WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ None 0x0 MFRQ None 0x1 NPWM None 0x2 MPWM None 0x3 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x2 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 TC_COUNT8 - CTRLC 8-bit Counter Mode - - Control C 0x6 8 read-write n 0x0 0xFFFFFFFF CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0x8 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Run Mode 0 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0xA 16 read-write n 0x0 0xFFFFFFFF EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Event Output Enable 8 1 TCEI TC Event Input 5 1 TCINV TC Inverted Event Input 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0xC 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0xD 8 read-write n 0x0 0xFFFFFFFF ERR Error Interrupt Enable 1 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 OVF Overflow Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0xFFFFFFFF ERR Error 1 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 OVF Overflow 0 1 SYNCRDY Synchronization Ready 3 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period Value 0x14 8 read-write n 0xFF 0xFFFFFFFF PER Period Value 0 8 TC_COUNT8 - READREQ 8-bit Counter Mode - - Read Request 0x2 16 read-write n 0x0 0xFFFFFFFF ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xF 8 read-only n 0x8 0xFFFFFFFF SLAVE Slave 4 1 read-only STOP Stop 3 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TCC0 Timer Counter Control 0 TCC 0x42002000 0x0 0x80 registers n TCC0 15 CC0 Compare and Capture 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CCB0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB0_DITH4 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB0_DITH5 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB0_DITH6 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB1_DITH4 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB1_DITH5 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB1_DITH6 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB2_DITH4 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB2_DITH5 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB2_DITH6 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB3_DITH4 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB3_DITH5 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB3_DITH6 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CCB0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB0_DITH4 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB0_DITH5 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB0_DITH6 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB1_DITH4 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB1_DITH5 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB1_DITH6 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB2_DITH4 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB2_DITH5 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB2_DITH6 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB3_DITH4 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB3_DITH5 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB3_DITH6 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 TCC_PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 TCC_PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 TCC_PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 TCC_PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC1 Timer Counter Control 1 TCC 0x42002400 0x0 0x80 registers n TCC1 16 CC0 Compare and Capture 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CCB0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB0_DITH4 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB0_DITH5 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB0_DITH6 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB1_DITH4 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB1_DITH5 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB1_DITH6 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB2_DITH4 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB2_DITH5 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB2_DITH6 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB3_DITH4 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB3_DITH5 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB3_DITH6 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CCB0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB0_DITH4 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB0_DITH5 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB0_DITH6 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB1_DITH4 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB1_DITH5 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB1_DITH6 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB2_DITH4 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB2_DITH5 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB2_DITH6 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB3_DITH4 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB3_DITH5 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB3_DITH6 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 TCC_PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 TCC_PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 TCC_PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 TCC_PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC2 Timer Counter Control 2 TCC 0x42002800 0x0 0x80 registers n TCC2 17 CC0 Compare and Capture 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture CC%s 0x44 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture CC%s 0x48 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture CC%s 0x4C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture CC%s 0x50 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 CCB0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB0_DITH4 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB0_DITH5 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB0_DITH6 Compare and Capture Buffer CCB%s 0x70 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB1_DITH4 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB1_DITH5 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB1_DITH6 Compare and Capture Buffer CCB%s 0x74 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB2_DITH4 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB2_DITH5 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB2_DITH6 Compare and Capture Buffer CCB%s 0x78 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 CCB3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 CCB3_DITH4 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 CCB3_DITH5 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 CCB3_DITH6 Compare and Capture Buffer CCB%s 0x7C 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 4 20 DITHERCY Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 5 19 DITHERCY Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0xFFFFFFFF CC Channel Compare/Capture Value 6 18 DITHERCY Dithering Cycle Number 0 6 TCC_CCB0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB0_DITH4 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB0_DITH5 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB0_DITH6 Compare and Capture Buffer CCB%s 0xE0 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB1_DITH4 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB1_DITH5 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB1_DITH6 Compare and Capture Buffer CCB%s 0x154 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB2_DITH4 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB2_DITH5 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB2_DITH6 Compare and Capture Buffer CCB%s 0x1CC 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_CCB3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 0 24 TCC_CCB3_DITH4 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 4 20 DITHERCYB Dithering Buffer Cycle Number 0 4 TCC_CCB3_DITH5 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 5 19 DITHERCYB Dithering Buffer Cycle Number 0 5 TCC_CCB3_DITH6 Compare and Capture Buffer CCB%s 0x248 32 read-write n 0x0 0xFFFFFFFF CCB Channel Compare/Capture Buffer Value 6 18 DITHERCYB Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0xFFFFFFFF COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0xFFFFFFFF ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 ENABLE Enable 1 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0xFFFFFFFF CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update of double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0xFFFFFFFF DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0xFFFFFFFF FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0xFFFFFFFF CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0xFFFFFFFF BLANK Fault A Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0xFFFFFFFF BLANK Fault B Blanking Mode 5 2 BLANKSelect NONE No blanking applied 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0xFFFFFFFF CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0xFFFFFFFF CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0xFFFFFFFF PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTB Pattern Buffer 0x64 16 read-write n 0x0 0xFFFFFFFF PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PER Period Value 0 24 TCC_PERB Period Buffer 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF PERB Period Buffer Value 0 24 TCC_PERB_DITH4 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 4 PERB Period Buffer Value 4 20 TCC_PERB_DITH5 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 5 PERB Period Buffer Value 5 19 TCC_PERB_DITH6 Period Buffer PERB 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCYB Dithering Buffer Cycle Number 0 6 PERB Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF DITHERCY Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x1 0xFFFFFFFF CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBV Pattern Buffer Valid 5 1 PERBV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only WAVEBV Wave Buffer Valid 6 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0xFFFFFFFF CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PATTB Pattern Buffer Busy 16 1 PER Period busy 7 1 PERB Period Buffer Busy 18 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 WAVEB Wave Buffer Busy 17 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0xFFFFFFFF CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WAVEB Waveform Control Buffer 0x68 32 read-write n 0x0 0xFFFFFFFF CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 CIPERENB Circular Period Enable Buffer 7 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 RAMPB Ramp Mode Buffer 4 2 RAMPBSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0xFFFFFFFF DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 USB Universal Serial Bus USB 0x41005000 0x0 0x1000 registers n USB 7 BINTERVAL0 HOST Bus Access Period of Pipe 0x103 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL1 HOST Bus Access Period of Pipe 0x123 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL2 HOST Bus Access Period of Pipe 0x143 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL3 HOST Bus Access Period of Pipe 0x163 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL4 HOST Bus Access Period of Pipe 0x183 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL5 HOST Bus Access Period of Pipe 0x1A3 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL6 HOST Bus Access Period of Pipe 0x1C3 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 BINTERVAL7 HOST Bus Access Period of Pipe 0x1E3 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 CTRLA Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 CTRLB HOST Control B 0x8 16 read-write n 0x0 0xFFFFFFFF BUSRESET Send USB Reset 9 1 DETACH Detach 0 1 GNAK Global NAK 9 1 L1RESUME Send L1 Resume 11 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 VBUSOK VBUS is OK 10 1 DADD DEVICE Device Address 0xA 8 read-write n 0x0 0xFFFFFFFF ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DESCADD Descriptor Address 0x24 32 read-write n 0x0 0xFFFFFFFF DESCADD Descriptor Address Value 0 32 DEVICE - CTRLA USB is Device - - Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 DEVICE - CTRLB USB is Device - - DEVICE Control B 0x8 16 read-write n 0x1 0xFFFFFFFF DETACH Detach 0 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect FS FS : Full Speed 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 DEVICE - DADD USB is Device - - DEVICE Device Address 0xA 8 read-write n 0x0 0xFFFFFFFF ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DEVICE - DESCADD USB is Device - - Descriptor Address 0x24 32 read-write n 0x0 0xFFFFFFFF DESCADD Descriptor Address Value 0 32 DEVICE - EPCFG0 USB is Device - - DEVICE End Point Configuration 0x200 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG1 USB is Device - - DEVICE End Point Configuration 0x320 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG2 USB is Device - - DEVICE End Point Configuration 0x460 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG3 USB is Device - - DEVICE End Point Configuration 0x5C0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG4 USB is Device - - DEVICE End Point Configuration 0x740 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG5 USB is Device - - DEVICE End Point Configuration 0x8E0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG6 USB is Device - - DEVICE End Point Configuration 0xAA0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPCFG7 USB is Device - - DEVICE End Point Configuration 0xC80 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE - EPINTENCLR0 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x210 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR1 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x338 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR2 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x480 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR3 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x5E8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR4 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x770 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR5 USB is Device - - DEVICE End Point Interrupt Clear Flag 0x918 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR6 USB is Device - - DEVICE End Point Interrupt Clear Flag 0xAE0 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENCLR7 USB is Device - - DEVICE End Point Interrupt Clear Flag 0xCC8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE - EPINTENSET0 USB is Device - - DEVICE End Point Interrupt Set Flag 0x212 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET1 USB is Device - - DEVICE End Point Interrupt Set Flag 0x33B 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET2 USB is Device - - DEVICE End Point Interrupt Set Flag 0x484 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET3 USB is Device - - DEVICE End Point Interrupt Set Flag 0x5ED 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET4 USB is Device - - DEVICE End Point Interrupt Set Flag 0x776 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET5 USB is Device - - DEVICE End Point Interrupt Set Flag 0x91F 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET6 USB is Device - - DEVICE End Point Interrupt Set Flag 0xAE8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTENSET7 USB is Device - - DEVICE End Point Interrupt Set Flag 0xCD1 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE - EPINTFLAG0 USB is Device - - DEVICE End Point Interrupt Flag 0x20E 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG1 USB is Device - - DEVICE End Point Interrupt Flag 0x335 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG2 USB is Device - - DEVICE End Point Interrupt Flag 0x47C 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG3 USB is Device - - DEVICE End Point Interrupt Flag 0x5E3 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG4 USB is Device - - DEVICE End Point Interrupt Flag 0x76A 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG5 USB is Device - - DEVICE End Point Interrupt Flag 0x911 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG6 USB is Device - - DEVICE End Point Interrupt Flag 0xAD8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTFLAG7 USB is Device - - DEVICE End Point Interrupt Flag 0xCBF 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE - EPINTSMRY USB is Device - - DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0xFFFFFFFF EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only DEVICE - EPSTATUS0 USB is Device - - DEVICE End Point Pipe Status 0x20C 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS1 USB is Device - - DEVICE End Point Pipe Status 0x332 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS2 USB is Device - - DEVICE End Point Pipe Status 0x478 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS3 USB is Device - - DEVICE End Point Pipe Status 0x5DE 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS4 USB is Device - - DEVICE End Point Pipe Status 0x764 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS5 USB is Device - - DEVICE End Point Pipe Status 0x90A 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS6 USB is Device - - DEVICE End Point Pipe Status 0xAD0 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUS7 USB is Device - - DEVICE End Point Pipe Status 0xCB6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only DEVICE - EPSTATUSCLR0 USB is Device - - DEVICE End Point Pipe Status Clear 0x208 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR1 USB is Device - - DEVICE End Point Pipe Status Clear 0x32C 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR2 USB is Device - - DEVICE End Point Pipe Status Clear 0x470 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR3 USB is Device - - DEVICE End Point Pipe Status Clear 0x5D4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR4 USB is Device - - DEVICE End Point Pipe Status Clear 0x758 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR5 USB is Device - - DEVICE End Point Pipe Status Clear 0x8FC 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR6 USB is Device - - DEVICE End Point Pipe Status Clear 0xAC0 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSCLR7 USB is Device - - DEVICE End Point Pipe Status Clear 0xCA4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only DEVICE - EPSTATUSSET0 USB is Device - - DEVICE End Point Pipe Status Set 0x20A 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET1 USB is Device - - DEVICE End Point Pipe Status Set 0x32F 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET2 USB is Device - - DEVICE End Point Pipe Status Set 0x474 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET3 USB is Device - - DEVICE End Point Pipe Status Set 0x5D9 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET4 USB is Device - - DEVICE End Point Pipe Status Set 0x75E 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET5 USB is Device - - DEVICE End Point Pipe Status Set 0x903 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET6 USB is Device - - DEVICE End Point Pipe Status Set 0xAC8 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - EPSTATUSSET7 USB is Device - - DEVICE End Point Pipe Status Set 0xCAD 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only DEVICE - FNUM USB is Device - - DEVICE Device Frame Number 0x10 16 read-only n 0x0 0xFFFFFFFF FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only DEVICE - FSMSTATUS USB is Device - - Finite State Machine Status 0xD 8 read-only n 0x1 0xFFFFFFFF FSMSTATE Fine State Machine Status 0 7 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 DEVICE - INTENCLR USB is Device - - DEVICE Device Interrupt Enable Clear 0x14 16 read-write n 0x0 0xFFFFFFFF EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTENSET USB is Device - - DEVICE Device Interrupt Enable Set 0x18 16 read-write n 0x0 0xFFFFFFFF EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTFLAG USB is Device - - DEVICE Device Interrupt Flag 0x1C 16 read-write n 0x0 0xFFFFFFFF EORSM End Of Resume 5 1 EORST End of Reset 3 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume 6 1 WAKEUP Wake Up 4 1 DEVICE - PADCAL USB is Device - - USB PAD Calibration 0x28 16 read-write n 0x0 0xFFFFFFFF TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 DEVICE - QOSCTRL USB is Device - - USB Quality Of Service 0x3 8 read-write n 0x5 0xFFFFFFFF CQOS Configuration Quality of Service 0 2 CQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Quality of Service 2 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DEVICE - STATUS USB is Device - - DEVICE Status 0xC 8 read-only n 0x40 0xFFFFFFFF LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 SPEED Speed Status 2 2 read-only SPEEDSelect FS Full-speed mode 0x0 HS High-speed mode 0x1 LS Low-speed mode 0x2 DEVICE - SYNCBUSY USB is Device - - Synchronization Busy 0x2 8 read-only n 0x0 0xFFFFFFFF ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only EPCFG0 DEVICE End Point Configuration 0x100 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG1 DEVICE End Point Configuration 0x120 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG2 DEVICE End Point Configuration 0x140 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG3 DEVICE End Point Configuration 0x160 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG4 DEVICE End Point Configuration 0x180 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG5 DEVICE End Point Configuration 0x1A0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG6 DEVICE End Point Configuration 0x1C0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPCFG7 DEVICE End Point Configuration 0x1E0 8 read-write n 0x0 0xFFFFFFFF EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPINTENCLR0 DEVICE End Point Interrupt Clear Flag 0x108 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR1 DEVICE End Point Interrupt Clear Flag 0x128 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR2 DEVICE End Point Interrupt Clear Flag 0x148 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR3 DEVICE End Point Interrupt Clear Flag 0x168 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR4 DEVICE End Point Interrupt Clear Flag 0x188 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR5 DEVICE End Point Interrupt Clear Flag 0x1A8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR6 DEVICE End Point Interrupt Clear Flag 0x1C8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENCLR7 DEVICE End Point Interrupt Clear Flag 0x1E8 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENSET0 DEVICE End Point Interrupt Set Flag 0x109 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET1 DEVICE End Point Interrupt Set Flag 0x129 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET2 DEVICE End Point Interrupt Set Flag 0x149 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET3 DEVICE End Point Interrupt Set Flag 0x169 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET4 DEVICE End Point Interrupt Set Flag 0x189 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET5 DEVICE End Point Interrupt Set Flag 0x1A9 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET6 DEVICE End Point Interrupt Set Flag 0x1C9 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTENSET7 DEVICE End Point Interrupt Set Flag 0x1E9 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTFLAG0 DEVICE End Point Interrupt Flag 0x107 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG1 DEVICE End Point Interrupt Flag 0x127 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG2 DEVICE End Point Interrupt Flag 0x147 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG3 DEVICE End Point Interrupt Flag 0x167 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG4 DEVICE End Point Interrupt Flag 0x187 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG5 DEVICE End Point Interrupt Flag 0x1A7 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG6 DEVICE End Point Interrupt Flag 0x1C7 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTFLAG7 DEVICE End Point Interrupt Flag 0x1E7 8 read-write n 0x0 0xFFFFFFFF RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0xFFFFFFFF EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only EPSTATUS0 DEVICE End Point Pipe Status 0x106 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS1 DEVICE End Point Pipe Status 0x126 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS2 DEVICE End Point Pipe Status 0x146 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS3 DEVICE End Point Pipe Status 0x166 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS4 DEVICE End Point Pipe Status 0x186 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS5 DEVICE End Point Pipe Status 0x1A6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS6 DEVICE End Point Pipe Status 0x1C6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUS7 DEVICE End Point Pipe Status 0x1E6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGLIN Data Toggle In 1 1 read-only DTGLOUT Data Toggle Out 0 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only EPSTATUSCLR0 DEVICE End Point Pipe Status Clear 0x104 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR1 DEVICE End Point Pipe Status Clear 0x124 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR2 DEVICE End Point Pipe Status Clear 0x144 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR3 DEVICE End Point Pipe Status Clear 0x164 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR4 DEVICE End Point Pipe Status Clear 0x184 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR5 DEVICE End Point Pipe Status Clear 0x1A4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR6 DEVICE End Point Pipe Status Clear 0x1C4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSCLR7 DEVICE End Point Pipe Status Clear 0x1E4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank Clear 2 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only EPSTATUSSET0 DEVICE End Point Pipe Status Set 0x105 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET1 DEVICE End Point Pipe Status Set 0x125 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET2 DEVICE End Point Pipe Status Set 0x145 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET3 DEVICE End Point Pipe Status Set 0x165 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET4 DEVICE End Point Pipe Status Set 0x185 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET5 DEVICE End Point Pipe Status Set 0x1A5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET6 DEVICE End Point Pipe Status Set 0x1C5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only EPSTATUSSET7 DEVICE End Point Pipe Status Set 0x1E5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only FLENHIGH HOST Host Frame Length 0x12 8 read-only n 0x0 0xFFFFFFFF FLENHIGH Frame Length 0 8 read-only FNUM HOST Host Frame Number 0x10 16 read-write n 0x0 0xFFFFFFFF FNCERR Frame Number CRC Error 15 1 read-only FNUM Frame Number 3 11 read-only MFNUM Micro Frame Number 0 3 read-only FSMSTATUS Finite State Machine Status 0xD 8 read-only n 0x1 0xFFFFFFFF FSMSTATE Fine State Machine Status 0 7 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 HOST - BINTERVAL0 USB is Host - - HOST Bus Access Period of Pipe 0x206 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL1 USB is Host - - HOST Bus Access Period of Pipe 0x329 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL2 USB is Host - - HOST Bus Access Period of Pipe 0x46C 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL3 USB is Host - - HOST Bus Access Period of Pipe 0x5CF 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL4 USB is Host - - HOST Bus Access Period of Pipe 0x752 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL5 USB is Host - - HOST Bus Access Period of Pipe 0x8F5 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL6 USB is Host - - HOST Bus Access Period of Pipe 0xAB8 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - BINTERVAL7 USB is Host - - HOST Bus Access Period of Pipe 0xC9B 8 read-write n 0x0 0xFFFFFFFF BITINTERVAL Bit Interval 0 8 HOST - CTRLA USB is Host - - Control A 0x0 8 read-write n 0x0 0xFFFFFFFF ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 HOST - CTRLB USB is Host - - HOST Control B 0x8 16 read-write n 0x0 0xFFFFFFFF BUSRESET Send USB Reset 9 1 L1RESUME Send L1 Resume 11 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 VBUSOK VBUS is OK 10 1 HOST - DESCADD USB is Host - - Descriptor Address 0x24 32 read-write n 0x0 0xFFFFFFFF DESCADD Descriptor Address Value 0 32 HOST - FLENHIGH USB is Host - - HOST Host Frame Length 0x12 8 read-only n 0x0 0xFFFFFFFF FLENHIGH Frame Length 0 8 read-only HOST - FNUM USB is Host - - HOST Host Frame Number 0x10 16 read-write n 0x0 0xFFFFFFFF FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 HOST - FSMSTATUS USB is Host - - Finite State Machine Status 0xD 8 read-only n 0x1 0xFFFFFFFF FSMSTATE Fine State Machine Status 0 7 read-only FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 HOST - HSOFC USB is Host - - HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0xFFFFFFFF FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 HOST - INTENCLR USB is Host - - HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0xFFFFFFFF DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 HSOF Host Start Of Frame Interrupt Disable 2 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 HOST - INTENSET USB is Host - - HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0xFFFFFFFF DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 HSOF Host Start Of Frame Interrupt Enable 2 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 HOST - INTFLAG USB is Host - - HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0xFFFFFFFF DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 HSOF Host Start Of Frame 2 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 HOST - PADCAL USB is Host - - USB PAD Calibration 0x28 16 read-write n 0x0 0xFFFFFFFF TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 HOST - PCFG0 USB is Host - - HOST End Point Configuration 0x200 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG1 USB is Host - - HOST End Point Configuration 0x320 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG2 USB is Host - - HOST End Point Configuration 0x460 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG3 USB is Host - - HOST End Point Configuration 0x5C0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG4 USB is Host - - HOST End Point Configuration 0x740 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG5 USB is Host - - HOST End Point Configuration 0x8E0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG6 USB is Host - - HOST End Point Configuration 0xAA0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PCFG7 USB is Host - - HOST End Point Configuration 0xC80 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST - PINTENCLR0 USB is Host - - HOST Pipe Interrupt Flag Clear 0x210 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR1 USB is Host - - HOST Pipe Interrupt Flag Clear 0x338 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR2 USB is Host - - HOST Pipe Interrupt Flag Clear 0x480 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR3 USB is Host - - HOST Pipe Interrupt Flag Clear 0x5E8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR4 USB is Host - - HOST Pipe Interrupt Flag Clear 0x770 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR5 USB is Host - - HOST Pipe Interrupt Flag Clear 0x918 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR6 USB is Host - - HOST Pipe Interrupt Flag Clear 0xAE0 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENCLR7 USB is Host - - HOST Pipe Interrupt Flag Clear 0xCC8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST - PINTENSET0 USB is Host - - HOST Pipe Interrupt Flag Set 0x212 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET1 USB is Host - - HOST Pipe Interrupt Flag Set 0x33B 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET2 USB is Host - - HOST Pipe Interrupt Flag Set 0x484 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET3 USB is Host - - HOST Pipe Interrupt Flag Set 0x5ED 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET4 USB is Host - - HOST Pipe Interrupt Flag Set 0x776 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET5 USB is Host - - HOST Pipe Interrupt Flag Set 0x91F 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET6 USB is Host - - HOST Pipe Interrupt Flag Set 0xAE8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTENSET7 USB is Host - - HOST Pipe Interrupt Flag Set 0xCD1 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST - PINTFLAG0 USB is Host - - HOST Pipe Interrupt Flag 0x20E 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG1 USB is Host - - HOST Pipe Interrupt Flag 0x335 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG2 USB is Host - - HOST Pipe Interrupt Flag 0x47C 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG3 USB is Host - - HOST Pipe Interrupt Flag 0x5E3 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG4 USB is Host - - HOST Pipe Interrupt Flag 0x76A 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG5 USB is Host - - HOST Pipe Interrupt Flag 0x911 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG6 USB is Host - - HOST Pipe Interrupt Flag 0xAD8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTFLAG7 USB is Host - - HOST Pipe Interrupt Flag 0xCBF 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST - PINTSMRY USB is Host - - HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0xFFFFFFFF EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only HOST - PSTATUS0 USB is Host - - HOST End Point Pipe Status 0x20C 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS1 USB is Host - - HOST End Point Pipe Status 0x332 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS2 USB is Host - - HOST End Point Pipe Status 0x478 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS3 USB is Host - - HOST End Point Pipe Status 0x5DE 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS4 USB is Host - - HOST End Point Pipe Status 0x764 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS5 USB is Host - - HOST End Point Pipe Status 0x90A 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS6 USB is Host - - HOST End Point Pipe Status 0xAD0 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUS7 USB is Host - - HOST End Point Pipe Status 0xCB6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only HOST - PSTATUSCLR0 USB is Host - - HOST End Point Pipe Status Clear 0x208 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR1 USB is Host - - HOST End Point Pipe Status Clear 0x32C 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR2 USB is Host - - HOST End Point Pipe Status Clear 0x470 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR3 USB is Host - - HOST End Point Pipe Status Clear 0x5D4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR4 USB is Host - - HOST End Point Pipe Status Clear 0x758 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR5 USB is Host - - HOST End Point Pipe Status Clear 0x8FC 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR6 USB is Host - - HOST End Point Pipe Status Clear 0xAC0 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSCLR7 USB is Host - - HOST End Point Pipe Status Clear 0xCA4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only HOST - PSTATUSSET0 USB is Host - - HOST End Point Pipe Status Set 0x20A 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET1 USB is Host - - HOST End Point Pipe Status Set 0x32F 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET2 USB is Host - - HOST End Point Pipe Status Set 0x474 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET3 USB is Host - - HOST End Point Pipe Status Set 0x5D9 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET4 USB is Host - - HOST End Point Pipe Status Set 0x75E 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET5 USB is Host - - HOST End Point Pipe Status Set 0x903 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET6 USB is Host - - HOST End Point Pipe Status Set 0xAC8 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - PSTATUSSET7 USB is Host - - HOST End Point Pipe Status Set 0xCAD 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only HOST - QOSCTRL USB is Host - - USB Quality Of Service 0x3 8 read-write n 0x5 0xFFFFFFFF CQOS Configuration Quality of Service 0 2 CQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Quality of Service 2 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 HOST - STATUS USB is Host - - HOST Status 0xC 8 read-write n 0x0 0xFFFFFFFF LINESTATE USB Line State Status 6 2 read-only SPEED Speed Status 2 2 HOST - SYNCBUSY USB is Host - - Synchronization Busy 0x2 8 read-only n 0x0 0xFFFFFFFF ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only HSOFC HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0xFFFFFFFF FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 INTENCLR HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0xFFFFFFFF DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Disable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 INTENSET HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0xFFFFFFFF DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Enable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 INTFLAG HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0xFFFFFFFF DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 EORSM End Of Resume 5 1 EORST End of Reset 3 1 HSOF Host Start Of Frame 2 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 PADCAL USB PAD Calibration 0x28 16 read-write n 0x0 0xFFFFFFFF TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 PCFG0 HOST End Point Configuration 0x100 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG1 HOST End Point Configuration 0x120 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG2 HOST End Point Configuration 0x140 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG3 HOST End Point Configuration 0x160 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG4 HOST End Point Configuration 0x180 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG5 HOST End Point Configuration 0x1A0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG6 HOST End Point Configuration 0x1C0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PCFG7 HOST End Point Configuration 0x1E0 8 read-write n 0x0 0xFFFFFFFF BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PINTENCLR0 HOST Pipe Interrupt Flag Clear 0x108 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR1 HOST Pipe Interrupt Flag Clear 0x128 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR2 HOST Pipe Interrupt Flag Clear 0x148 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR3 HOST Pipe Interrupt Flag Clear 0x168 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR4 HOST Pipe Interrupt Flag Clear 0x188 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR5 HOST Pipe Interrupt Flag Clear 0x1A8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR6 HOST Pipe Interrupt Flag Clear 0x1C8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENCLR7 HOST Pipe Interrupt Flag Clear 0x1E8 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Disable 3 1 STALL Stall Interrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENSET0 HOST Pipe Interrupt Flag Set 0x109 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET1 HOST Pipe Interrupt Flag Set 0x129 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET2 HOST Pipe Interrupt Flag Set 0x149 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET3 HOST Pipe Interrupt Flag Set 0x169 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET4 HOST Pipe Interrupt Flag Set 0x189 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET5 HOST Pipe Interrupt Flag Set 0x1A9 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET6 HOST Pipe Interrupt Flag Set 0x1C9 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTENSET7 HOST Pipe Interrupt Flag Set 0x1E9 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTFLAG0 HOST Pipe Interrupt Flag 0x107 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG1 HOST Pipe Interrupt Flag 0x127 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG2 HOST Pipe Interrupt Flag 0x147 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG3 HOST Pipe Interrupt Flag 0x167 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG4 HOST Pipe Interrupt Flag 0x187 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG5 HOST Pipe Interrupt Flag 0x1A7 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG6 HOST Pipe Interrupt Flag 0x1C7 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTFLAG7 HOST Pipe Interrupt Flag 0x1E7 8 read-write n 0x0 0xFFFFFFFF PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTSMRY HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0xFFFFFFFF EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only PSTATUS0 HOST End Point Pipe Status 0x106 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS1 HOST End Point Pipe Status 0x126 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS2 HOST End Point Pipe Status 0x146 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS3 HOST End Point Pipe Status 0x166 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS4 HOST End Point Pipe Status 0x186 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS5 HOST End Point Pipe Status 0x1A6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS6 HOST End Point Pipe Status 0x1C6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUS7 HOST End Point Pipe Status 0x1E6 8 read-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only CURBK Current Bank 2 1 read-only DTGL Data Toggle 0 1 read-only PFREEZE Pipe Freeze 4 1 read-only PSTATUSCLR0 HOST End Point Pipe Status Clear 0x104 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR1 HOST End Point Pipe Status Clear 0x124 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR2 HOST End Point Pipe Status Clear 0x144 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR3 HOST End Point Pipe Status Clear 0x164 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR4 HOST End Point Pipe Status Clear 0x184 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR5 HOST End Point Pipe Status Clear 0x1A4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR6 HOST End Point Pipe Status Clear 0x1C4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSCLR7 HOST End Point Pipe Status Clear 0x1E4 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only CURBK Curren Bank clear 2 1 write-only DTGL Data Toggle clear 0 1 read-only PFREEZE Pipe Freeze Clear 4 1 write-only PSTATUSSET0 HOST End Point Pipe Status Set 0x105 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET1 HOST End Point Pipe Status Set 0x125 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET2 HOST End Point Pipe Status Set 0x145 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET3 HOST End Point Pipe Status Set 0x165 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET4 HOST End Point Pipe Status Set 0x185 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET5 HOST End Point Pipe Status Set 0x1A5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET6 HOST End Point Pipe Status Set 0x1C5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only PSTATUSSET7 HOST End Point Pipe Status Set 0x1E5 8 write-only n 0x0 0xFFFFFFFF BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only CURBK Current Bank Set 2 1 write-only DTGL Data Toggle Set 0 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only QOSCTRL USB Quality Of Service 0x3 8 read-write n 0x5 0xFFFFFFFF CQOS Configuration Quality of Service 0 2 CQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Quality of Service 2 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 STATUS HOST Status 0xC 8 read-write n 0x0 0xFFFFFFFF LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 SPEED Speed Status 2 2 read-only SPEEDSelect FS Full-speed mode 0x0 HS High-speed mode 0x1 LS Low-speed mode 0x2 SYNCBUSY Synchronization Busy 0x2 8 read-only n 0x0 0xFFFFFFFF ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only WDT Watchdog Timer WDT 0x40001000 0x0 0x10 registers n WDT 2 CLEAR Clear 0x8 8 write-only n 0x0 0xFFFFFFFF CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5 CONFIG Configuration 0x1 8 read-write n 0xBB 0xFFFFFFFF PER Time-Out Period 0 4 PERSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb CTRL Control 0x0 8 read-write n 0x0 0xFFFFFFFF ALWAYSON Always-On 7 1 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 EWCTRL Early Warning Interrupt Control 0x2 8 read-write n 0xB 0xFFFFFFFF EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect 8 8 clock cycles 0x0 16 16 clock cycles 0x1 32 32 clock cycles 0x2 64 64 clock cycles 0x3 128 128 clock cycles 0x4 256 256 clock cycles 0x5 512 512 clock cycles 0x6 1K 1024 clock cycles 0x7 2K 2048 clock cycles 0x8 4K 4096 clock cycles 0x9 8K 8192 clock cycles 0xa 16K 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0xFFFFFFFF EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0xFFFFFFFF EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0xFFFFFFFF EW Early Warning 0 1 STATUS Status 0x7 8 read-only n 0x0 0xFFFFFFFF SYNCBUSY Synchronization Busy 7 1 read-only